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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">GICC_STATUSR, CPU Interface Status Register</h1><p>The GICC_STATUSR characteristics are:</p><h2>Purpose</h2>
        <p>Provides software with a mechanism to detect:</p>

      
        <ul>
<li>Accesses to reserved locations.
</li><li>Writes to read-only locations.
</li><li>Reads of write-only locations.
</li></ul>
      <h2>Configuration</h2><p>This register is present only when FEAT_GICv3_LEGACY is implemented. Otherwise, direct accesses to GICC_STATUSR are <span class="arm-defined-word">RES0</span>.</p>
        <p>If the GIC implementation supports two Security states this register is Banked to provide Secure and Non-secure copies.</p>

      
        <p>This register is used only when System register access is not enabled. If System register access is enabled, this register is not updated. Equivalent functionality might be provided by appropriate traps and exceptions.</p>
      <h2>Attributes</h2>
        <p>GICC_STATUSR is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="27"><a href="#fieldset_0-31_5">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-4_4">ASV</a></td><td class="lr" colspan="1"><a href="#fieldset_0-3_3">WROD</a></td><td class="lr" colspan="1"><a href="#fieldset_0-2_2">RWOD</a></td><td class="lr" colspan="1"><a href="#fieldset_0-1_1">WRD</a></td><td class="lr" colspan="1"><a href="#fieldset_0-0_0">RRD</a></td></tr></tbody></table><h4 id="fieldset_0-31_5">Bits [31:5]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-4_4">ASV, bit [4]</h4><div class="field">
      <p>Attempted security violation.</p>
    <table class="valuetable"><tr><th>ASV</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Normal operation.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>A Non-secure access to a Secure register has been detected.</p>
        </td></tr></table>
      <div class="note"><span class="note-header">Note</span>
        <p>This bit is not set to 1 for registers where any of the fields are Non-secure.</p>
      </div>
    </div><h4 id="fieldset_0-3_3">WROD, bit [3]</h4><div class="field">
      <p>Write to an RO location.</p>
    <table class="valuetable"><tr><th>WROD</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Normal operation.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>A write to an RO location has been detected.</p>
        </td></tr></table>
      <p>When a violation is detected, software must write 1 to this register to reset it.</p>
    </div><h4 id="fieldset_0-2_2">RWOD, bit [2]</h4><div class="field">
      <p>Read of a WO location.</p>
    <table class="valuetable"><tr><th>RWOD</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Normal operation.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>A read of a WO location has been detected.</p>
        </td></tr></table>
      <p>When a violation is detected, software must write 1 to this register to reset it.</p>
    </div><h4 id="fieldset_0-1_1">WRD, bit [1]</h4><div class="field">
      <p>Write to a reserved location.</p>
    <table class="valuetable"><tr><th>WRD</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Normal operation.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>A write to a reserved location has been detected.</p>
        </td></tr></table>
      <p>When a violation is detected, software must write 1 to this register to reset it.</p>
    </div><h4 id="fieldset_0-0_0">RRD, bit [0]</h4><div class="field">
      <p>Read of a reserved location.</p>
    <table class="valuetable"><tr><th>RRD</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Normal operation.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>A read of a reserved location has been detected.</p>
        </td></tr></table>
      <p>When a violation is detected, software must write 1 to this register to reset it.</p>
    </div><h2>Accessing GICC_STATUSR</h2>
        <p>This is an optional register. If the register is not implemented, the location is RAZ/WI.</p>

      
        <p>If this register is implemented, <a href="ext-gicv_statusr.html">GICV_STATUSR</a> must also be implemented.</p>
      <h4>GICC_STATUSR can be accessed through the memory-mapped interfaces:</h4><table class="info"><tr><th>Component</th><th>Offset</th><th>Instance</th></tr><tr><td>GIC CPU interface</td><td><span class="hexnumber">0x002C</span></td><td>GICC_STATUSR (S)</td></tr></table><p>This interface is accessible as follows:</p><ul><li>When GICD_CTLR.DS == 0, accesses to this register are <span class="access_level">RW</span>.
          </li><li>When an access is Secure, accesses to this register are <span class="access_level">RW</span>.
          </li></ul><table class="info"><tr><th>Component</th><th>Offset</th><th>Instance</th></tr><tr><td>GIC CPU interface</td><td><span class="hexnumber">0x002C</span></td><td>GICC_STATUSR (NS)</td></tr></table><p>This interface is accessible as follows:</p><ul><li>When GICD_CTLR.DS == 0, accesses to this register are <span class="access_level">RW</span>.
          </li><li>When an access is Non-secure, accesses to this register are <span class="access_level">RW</span>.
          </li></ul><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:07; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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